18 lines
264 B
Systemverilog
18 lines
264 B
Systemverilog
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//
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// Copyright (c) 2026 Mirocom Laboratories and MSP engineers.
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// All Rights Reserved.
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//
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//
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// MSP System-on-Chip description
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//
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// @clk_i: Clock input
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// @reset_i: Reset input
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//
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module soc (
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input wire clk_i,
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input wire reset_i
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);
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endmodule
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