commit ae3e9b26c11071e939e933d851bceb6e4a6f0808
Author: Ian Moffett <ian@mirocom.org>
Date:   Sun May 24 01:08:46 2026 -0400

    initial commit
    
    Signed-off-by: Ian Moffett <ian@mirocom.org>

diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..67852ef
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,4 @@
+*.o
+*.d
+*.vcd
+obj_dir
diff --git a/chipset/rtl/soc.sv b/chipset/rtl/soc.sv
new file mode 100644
index 0000000..8d44231
--- /dev/null
+++ b/chipset/rtl/soc.sv
@@ -0,0 +1,17 @@
+//
+// Copyright (c) 2026 Mirocom Laboratories and MSP engineers.
+// All Rights Reserved.
+//
+
+//
+// MSP System-on-Chip description
+//
+// @clk_i:      Clock input
+// @reset_i:    Reset input
+//
+module soc (
+    input wire clk_i,
+    input wire reset_i
+);
+
+endmodule
diff --git a/chipset/tb/.gitignore b/chipset/tb/.gitignore
new file mode 100644
index 0000000..e204dd3
--- /dev/null
+++ b/chipset/tb/.gitignore
@@ -0,0 +1 @@
+obj_dir
diff --git a/chipset/tb/Makefile b/chipset/tb/Makefile
new file mode 100644
index 0000000..37c9264
--- /dev/null
+++ b/chipset/tb/Makefile
@@ -0,0 +1,31 @@
+#
+# Copyright (c) 2026 Mirocom Laboratories and MSP engineers.
+# All Rights Reserved.
+#
+
+TB_BIN = verilator
+TB_FLAGS = \
+		-Wall 				 \
+		-Wno-UNUSED			 \
+		-DMENSIA_SIM	 	 \
+		--trace 			 \
+		-cc 				 \
+		-I../rtl/inc		 \
+		$(SV_FILES) 		 \
+		--exe $(TB_FILES) 	 \
+		--top-module soc
+
+SV_FILES = $(shell find ../rtl/ -name "*.sv")
+TB_FILES = $(shell find . -name "*.cc")
+
+.PHONY: all
+all: obj vcd
+
+.PHONY: obj
+obj:
+	$(TB_BIN) $(TB_FLAGS)
+
+.PHONY: vcd
+vcd:
+	make -C obj_dir/ -f Vsoc.mk Vsoc
+	./obj_dir/Vsoc
diff --git a/chipset/tb/test_core.cc b/chipset/tb/test_core.cc
new file mode 100644
index 0000000..ab74382
--- /dev/null
+++ b/chipset/tb/test_core.cc
@@ -0,0 +1,52 @@
+//
+// Copyright (c) 2026 Mirocom Laboratories and MSP engineers.
+// All Rights Reserved.
+//
+
+#include <stdlib.h>
+#include <iostream>
+#include <verilated.h>
+#include <verilated_vcd_c.h>
+#include "Vsoc.h"
+#include "Vsoc___024root.h"
+
+#define MAX_SIM_ITER 1000
+
+int main(int argc, char** argv, char** env)
+{
+    Vsoc *soc = new Vsoc;
+
+    Verilated::traceEverOn(true);
+    VerilatedVcdC *m_trace = new VerilatedVcdC;
+    soc->trace(m_trace, 5);
+    m_trace->open("soc.vcd");
+
+    soc->clk_i = 0;
+    soc->reset_i = 1;           /* ACTIVE-LOW */
+
+    for (int i = 0; i < MAX_SIM_ITER; ++i) {
+        soc->eval();
+        m_trace->dump(i);
+
+        switch (i) {
+        case 0:
+            soc->reset_i = 0;
+            break;
+        case 3:
+            break;
+        case 5:
+            soc->reset_i = 1;
+            break;
+        case 6:
+            break;
+        case 10:
+            break;
+        }
+
+        soc->clk_i ^= 1;
+    }
+
+    m_trace->close();
+    delete soc;
+    return 0;
+}