initial commit

Signed-off-by: Ian Moffett <ian@mirocom.org>

chipset/rtl/soc.sv

@@ -0,0 +1,17 @@
+//
+// Copyright (c) 2026 Mirocom Laboratories and MSP engineers.
+// All Rights Reserved.
+//
+
+//
+// MSP System-on-Chip description
+//
+// @clk_i:      Clock input
+// @reset_i:    Reset input
+//
+module soc (
+    input wire clk_i,
+    input wire reset_i
+);
+
+endmodule