18 lines
264 B
Systemverilog
18 lines
264 B
Systemverilog
//
|
|
// Copyright (c) 2026 Mirocom Laboratories and MSP engineers.
|
|
// All Rights Reserved.
|
|
//
|
|
|
|
//
|
|
// MSP System-on-Chip description
|
|
//
|
|
// @clk_i: Clock input
|
|
// @reset_i: Reset input
|
|
//
|
|
module soc (
|
|
input wire clk_i,
|
|
input wire reset_i
|
|
);
|
|
|
|
endmodule
|